This disclosure relates to one-time programmable bitcell, and more specifically to a one-time programmable bitcell with reduced leakage at its select device.
The Internet of Things (IoT) is an emerging market in the semiconductor industry.
The IoT is a network of internetworked smart devices. The category of IoT smart devices includes any devices that are networked together and are not traditional computers. Examples of smart devices include home automation (thermostats, security, lighting, home appliances, etc.), biochip transponders on animals, Radio-frequency identification (RFID) chips for inventory control, and many other types of devices. Many of these devices require non-volatile memory (NVM). Many IoT devices have limited power supplies such as small batteries; as another example, RFID chips typically extract power from the radio waves sent by the RFID reader. This creates a need for a very low power NVM embedded memory. The NVM can be used to store code (e.g., firmware) in IoT chips, record history from a sensor (e.g., an RFID chip that records temperature during the transport of some item), store the history of an animal with a biochip transponder, and for many other applications.
One-Time Programmable (OTP) Gate Oxide rupture memories can be used as NVM on IoT devices. OTP Gate Oxide memories typically include an anti-fuse device having a thin oxide layer and a select device having a thicker oxide layer. The anti-fuse and select devices are connected in series. OTP Gate Oxide memories typically use an electric field of around 30 MV/cm to rupture anti-fuses in the thin oxide of the anti-fuse devices. This 30 MV/cm is a compromise voltage that balances the demands of programming speeds and stresses on the chip. Many applications program the OTP memory at test, and testing time is a significant portion of the total manufacturing cost of a chip. Using higher voltages reduces the programming time, thus reducing test costs and overall manufacturing cost. Typically, 30 MV/cm provides a reasonable programming time and tolerable amount of stress on the peripheral devices.
When a selected bitcell is being programmed, an inhibit voltage can be applied to the drain of all bitcells connected to the same select device and anti-fuse device as the bitcell being programmed. This inhibit voltage prevents the connected bitcells from accidentally rupturing during programming of the bitcell selected for programming. In a typical 55 nm 1.2V/2.5V process, 30 MV/cm on the 1.2V device is around an 8.7V rupture voltage, and the inhibit voltage may be around 2.9V, or one-third of the rupture voltage. The inhibit voltage is supplied by a bitline, which connects bitcells running along a direction perpendicular to the direction of the select device and anti-fuse device. The unselected bitcells connected to an inhibited bitcell via the bitline are being neither programmed nor inhibited, and their NMOS select devices and anti-fuse devices are grounded. The 2.9V supplied to the drain of these otherwise grounded bitcells is higher than the specified power supply voltage of 2.5V. Applying a 2.9V bitline voltage to the drain of a select device with a grounded gate can lead to gate induced drain leakage (GIDL). GIDL is a leakage current that occurs due to a high electric field between the gate and the drain. Since a NVM device can have many bitcells connected to each select device and anti-fuse device, and many bitcells along each bitline, the number of bitcells that receive the inhibit voltage at a grounded select gate, and thus exhibit GIDL, can be quite high, creating a lot of leakage within the NVM device.
Applying a lower inhibit voltage (e.g., 2.5V) to the bitline will reduce the GIDL, but this lower voltage will increase the stress on the bitcells being inhibited. This can lead to unwanted programming events or latent gate oxide damage in the inhibited bitcells, which is problematic for high-reliability products. Latent gate oxide damage causes an oxide to rupture later with low stress. Low stress can be the stress the oxide seeing during a normal read operation. Other previous solutions to address GIDL include supplying a high current to the unselected devices, breaking up an array of bitcells to reduce the number of devices producing GIDL, and placing two select devices in series to create a gate cascode. However, running a high current consumes power, which is undesirable for lower power IoT applications. Breaking up an array of bitcells and using a gate cascode both increase the size of the NVM, which is also undesirable.